1. Field of the Invention
The present invention relates to phase change memories and control methods thereof.
2. Description of the Related Art
A memory composed of a plurality of phase change storage elements is named Phase Change Memory (PCM). The phase change storage element may be in a crystalline state or in an amorphous state. The state of the phase change storage element is dependent on the value of an input current flowing through the phase change storage element and an active period of the input current. In a situation wherein the input current is great and the active period is short, the phase change storage element is set to the amorphous state and has high impedance. The phase change storage element in the amorphous state is under a reset mode, and the high impedance represents datum ‘1.’ In another situation wherein the input current is low and the active period is long, the phase change storage element may be set to the crystalline state and has low impedance. The phase change storage element in the crystalline state is under a set mode and the low impedance represents datum ‘0.’
FIG. 1 illustrates the circuit of one bit of a conventional phase change memory, which comprises a current source 102, a phase change storage element PCR, a switch SW, a control module 104 and a comparator comp. The current source 102 provides an input current Is and is controlled by the control module 104. The control module 104 further controls the state of the switch SW. To store data ‘1’ into the phase change storage element PCR, the control module 104 sets the input current Is equal to a reset mode current and turns on the switch SW for a reset mode time interval. Thus, the phase change storage element PCR is set to the reset mode and has great impedance representing datum ‘1.’ To store datum ‘0’ into the phase change element PCR, the control module 104 sets the input current Is equal to a set mode current and turns on the switch SW for a set mode time interval. Thus, the phase change storage element PCR is set to the set mode and has a low impedance represented as datum ‘0.’ To read datum from the phase change storage element PCR, the control module 104 turns on the switch SW and sets the input current Is equal to a read current. The input current Is flows through the phase change storage element PCR to generate an output voltage relating to the impedance of the PCR. The output voltage is sent to the comparator comp to be compared with a reference voltage Vref. The comparison result is used in determining the datum stored in the phase change storage element PCR. If the output voltage is greater than the reference voltage Vref, the phase change storage element PCR has great impedance and the datum stored in the phase change storage element PCR is ‘1.’ If the output voltage is lower than the reference voltage Vref, the phase change storage element PCR has low impedance and the datum stored therein is ‘0’. In the aforementioned description, the read current is far lower than the set mode current, and the set mode current is much lower than the reset mode current. Furthermore, the set mode time interval is longer than the reset mode time interval.
Each bit of a conventional phase change memory, however, has to be individually equipped with a circuit as shown in FIG. 1. Thus, a large circuit board is required and the operating efficiency of the phase change memory is poor. As such, novel phase change memories with a small-sized circuit, good operating efficiency and low power consumption are called for.